#ifndef HW_SCI_H
#define HW_SCI_H

//*************************************************************************************************
//
// The following are defines for the SCI register offsets
//
//*************************************************************************************************
#define SCI_O_RBR     0x00U // Receive Buffer Register
#define SCI_O_THR     0x00U // Transmit Holding Register
#define SCI_O_DLL     0x00U // Divisor Latch Low Register
#define SCI_O_DLH     0x04U // Divisor Latch High Register
#define SCI_O_IER     0x04U // Interrupt Enable Register
#define SCI_O_IIR     0x08U // Interrupt Identity Register
#define SCI_O_FCR     0x08U // FIFO Control Register
#define SCI_O_LCR     0x0CU // Line Control Register
#define SCI_O_MCR     0x10U // Modem Control Register
#define SCI_O_LSR     0x14U // Line Status Register
#define SCI_O_MSR     0x18U // Modem Status Register
#define SCI_O_SCR     0x1CU // Scratchpad Register
#define SCI_O_USR     0x7CU // UART Status Register
#define SCI_O_TFL     0x80U // Transmit FIFO Level Register
#define SCI_O_RFL     0x84U // Receive FIFO Level Register
#define SCI_O_HTX     0xA4U // Halt TX Register
#define SCI_O_DAMSA   0xA8U // DMA Software Acknowledge Register
#define SCI_O_DLF     0xC0U // Divisor Latch Fraction Register
#define SCI_O_RAR     0xC4U // Receive Address Register
#define SCI_O_TAR     0xC8U // Transmit Address Register
#define SCI_O_LCR_EXT 0xCCU // Line Extended Control Register

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRBR register
//
//*************************************************************************************************
#define SCI_IER_ERBFI 0x1U
#define SCI_IER_ETBEI 0x2U
#define SCI_IER_ELSI  0x4U
#define SCI_IER_EDSSI 0x8U
#define SCI_IER_PTIME 0x80U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIIIR register
//
//*************************************************************************************************
#define SCI_IIR_INTID_S   0x0U
#define SCI_IIR_INTID_M   0xFU
#define SCI_IIR_RESERVE_S 4U
#define SCI_IIR_RESERVE_M 0x30U
#define SCI_IIR_FIFO_EN_S 6U
#define SCI_IIR_FIFO_EN_M 0xC0U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFCR register
//
//*************************************************************************************************
#define SCI_FCR_FIFOE  0x1U
#define SCI_FCR_RFIFOR 0x2U
#define SCI_FCR_XFIFOR 0x4U
#define SCI_FCR_TET_S  4U
#define SCI_FCR_TET_M  0x30U
#define SCI_FCR_RCVR_S 6U
#define SCI_FCR_RCVR_M 0xC0U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILCR register
//
//*************************************************************************************************
#define SCI_LCR_DLS_S        0U
#define SCI_LCR_DLS_M        0x3U
#define SCI_LCR_STOP         0x4U
#define SCI_LCR_PEN          0x8U
#define SCI_LCR_EPS          0x10U
#define SCI_LCR_STICK_PARITY 0x20U
#define SCI_LCR_BC           0x40U
#define SCI_LCR_DLAB         0x80U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIMCR register
//
//*************************************************************************************************
#define SCI_MCR_LOOPBACK 0x10U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILSR register
//
//*************************************************************************************************
#define SCI_LSR_DR   0x1U
#define SCI_LSR_OE   0x2U
#define SCI_LSR_PE   0x4U
#define SCI_LSR_FE   0x8U
#define SCI_LSR_BI   0x10U
#define SCI_LSR_THRE 0x20U
#define SCI_LSR_TEMT 0x40U
#define SCI_LSR_RFE  0x80U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIMSR register
//
//*************************************************************************************************
#define SCI_MSR_DCTS 0x1U
#define SCI_MSR_DDSR 0x2U
#define SCI_MSR_TERI 0x4U
#define SCI_MSR_DDCD 0x8U
#define SCI_MSR_CTS  0x10U
#define SCI_MSR_DSR  0x20U
#define SCI_MSR_RI   0x40U
#define SCI_MSR_DCD  0x80U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIUSR register
//
//*************************************************************************************************
#define SCI_USR_BUSY 0x1U
#define SCI_USR_TFNF 0x2U
#define SCI_USR_TFE  0x4U
#define SCI_USR_RFNE 0x8U
#define SCI_USR_RFF  0x10U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITFL register
//
//*************************************************************************************************
#define SCI_TFL_TFL_S 0U
#define SCI_TFL_TFL_M 0x1FU

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRFL register
//
//*************************************************************************************************
#define SCI_RFL_RFL_S 0U
#define SCI_RFL_RFL_M 0x1FU

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIHTX register
//
//*************************************************************************************************
#define SCI_HTX_HTX 0x1U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIDMASA register
//
//*************************************************************************************************
#define SCI_DMSA_DMASA 0x1U

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILCR_EXT register
//
//*************************************************************************************************
#define SCI_LCR_EXT_DLS_E         0x1U
#define SCI_LCR_EXT_ADDR_MATCH    0x2U
#define SCI_LCR_EXT_SEND_ADDR     0x4U
#define SCI_LCR_EXT_TRANSMIT_MODE 0x8U

#endif
